Re: Questions regarding adding a patch in linux/drivers/char/8250.c

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On Mon, May 21, 2012 at 4:30 AM, Alan Cox <alan@xxxxxxxxxxxxxxxxxxx> 
wrote:
> On Mon, 21 May 2012 14:19:34 +0800
> "Donald" <donald@xxxxxxxxxxx> wrote:
>
>> Hi,
>>
>> This is Donald from ASIX Electronics Corp. My company has three PCI to 
Serial controllers, including MCS9845, MCS9835, and MCS9820.
>> Currently those serial devices using these three chips can directly use 
the Linux kernel's serial driver in
>> linux/drivers/char/8250.c. Recently we find these three chips have a 
hardware bug relating to parity error count function. We have a
>> software workaround for this issue. Below for reference is a pseudo 
code for this workaround.
>
> Actually I have a second question.
>
> Would it not be better to set the device to 8N1 and do the parity in
> software rather than lose the FIFO, especially at higher speeds ? Can 
you
> clarify what the erratum is triggered by ?
>
> Alan


I saw your suggestion and thought it could work for a UART we are working 
with as well, which cannot identify which bytes have parity errors. 
However, It seems that doing parity in software would be a fine solution 
if you are using less than 8 data bits, but would not work with 8 bits + 
parity. Unless the UART supports 9 data bits, you would be unable to read 
the parity byte from the UART, and would still have the same problem.

-Jason




From:   Alan Cox <alan@xxxxxxxxxxxxxxxxxxx>
To:     "Donald" <donald@xxxxxxxxxxx>
Cc:     <linux-serial@xxxxxxxxxxxxxxx>
Date:   05/21/2012 04:29 AM
Subject:        Re: Questions regarding adding a patch in 
linux/drivers/char/8250.c
Sent by:        linux-serial-owner@xxxxxxxxxxxxxxx



On Mon, 21 May 2012 14:19:34 +0800
"Donald" <donald@xxxxxxxxxxx> wrote:

> Hi,
> 
> This is Donald from ASIX Electronics Corp. My company has three PCI to 
Serial controllers, including MCS9845, MCS9835, and MCS9820.
> Currently those serial devices using these three chips can directly use 
the Linux kernel's serial driver in
> linux/drivers/char/8250.c. Recently we find these three chips have a 
hardware bug relating to parity error count function. We have a
> software workaround for this issue. Below for reference is a pseudo code 
for this workaround.

Actually I have a second question.

Would it not be better to set the device to 8N1 and do the parity in
software rather than lose the FIFO, especially at higher speeds ? Can you
clarify what the erratum is triggered by ?

Alan


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