>>>>> "John" == John Linn <john.linn@xxxxxxxxxx> writes: John> From: XAQ IP Librarian <abq_iplib@xaqiptest40.(none)> John> Byte accesses for I/O devices in Xilinx IP is going to be less John> desired in the future such that the driver is being changed to John> use 32 bit accesses. Why is it less desired? Back when I wrote the driver, I used 8bit access on purpose to be independent of register widths / endianess. We have used the driver on systems where (something looking like) a uartlite was behind a 16bit bus, so doing 32bit accesses would require double the bus accesses. Btw, the abq_iplib@xaqiptest40 address is (obviously) invalid. -- Bye, Peter Korsgaard -- To unsubscribe from this list: send the line "unsubscribe linux-serial" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
