>>>>> "David" == David H Lynch <dhlii@xxxxxxxxxx> writes: Hi, David> You force the port regshift value to 2 in your init code, David> but then you ignore it and hard code the register offsets David> preshifted. Yes, the regshift value is not used by the driver, I just kept the initialization as documentation. The Xilinx IP block afaik cannot be configured with a different regshift value than 2, so I hardcoded it. We can change that if it would ever be a problem, but there's unfortunately no clean way of representing this in the device/ressource data, so I would prefer to leave that out unless it's needed. David> Also there is no provision for running the UartLite without David> using interrupts. The Pico E12/E14 frequently use FPGA David> firmare that does not include a PIC. Some implimentations of David> the UartLite use dcr instead of memory mapped ports. No - again like the early serial stuff that's something that can be added once the base driver is mainlined if there's demand. Does polling even work decently with the small fifo size of the uartlite? -- Bye, Peter Korsgaard - To unsubscribe from this list: send the line "unsubscribe linux-serial" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
