On Sun, 29 Nov 2015, Ondrej Zary wrote:
> > [...] I think that this should solve the problem:
>
> Yes, it does!
>
> [ 48.119367] scsi host2: Generic NCR5380/NCR53C400 SCSI, io_port 0x0, n_io_port 0, base 0xd8000, irq 0, can_queue 16, cmd_per_lun 2, sg_tablesize 128, this_id 7, flags { NO_DMA_FIXUP }, options { AUTOPROBE_IRQ PSEUDO_DMA }
> [ 49.715388] scsi 2:0:1:0: Direct-Access QUANTUM LP240S GM240S01X 4.6 PQ: 0 ANSI: 2 CCS
That still takes about 1.6 seconds to scan a vacant bus ID. It should be
more like 0.25 seconds. Did you have the entire patch series applied?
The code presently in mainline spins for 500 iterations in the relevant
busy-wait loop, with the comment, "8uS a cycle for the cpu access". That
doesn't help me much. Does that refer to an ISA bus cycle? Or one
iteration of the loop? Electrical conductance?
If we knew how many loops_per_jiffy your machine gets, and your CONFIG_HZ
value, we could figure out how long a chip register access takes (which
might be 8 us).
I'll try to figure out a similar timing for my Domex PCI card to see if
there is some sort of compromise to be found.
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