On Tue, May 26, 2009 at 9:49 AM, Michael Chan <mchan@xxxxxxxxxxxx> wrote: ... > Hi Grant, these are what we call "DMA control structures" as opposed to > DMA packet data. Our chips are configured to do an additional 32-bit > endian swap on all DMA control structures. This way, all 32-bit control > fields (such as length, status, etc) will come out right when the driver > reads these fields. > > If everything was defined as u32 in all these control structures, we > wouldn't have to add the #ifdef. u8 and u16 fields have to be defined > this way or else big endian CPUs would read the wrong offset. > > If you look at some of the control structures in tg3.h, you'll see the > same thing. Ah ok...so the chip is programmed configured to know about host endianess. I'm familiar with tg3 having that and just hadn't noticed it here yet. thanks, grant -- To unsubscribe from this list: send the line "unsubscribe linux-scsi" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
