Moore, Eric wrote:
On Tuesday, March 03, 2009 2:29 PM, James Bottomley wrote:
On Wed, 2009-02-25 at 14:12 -0700, Matthew Wilcox wrote:
On Wed, Feb 25, 2009 at 01:27:00PM -0700, Moore, Eric wrote:
What are you suggesting? Calling wmb()?
PCI writes can be posted, so the him_register writel() may
not complete
for a few thousand cycles. wmb() isn't going to solve the
problem. A
readl() from the device would, as would your current solution of
ignoring subsequent interrupts.
This seems to be the most serious issue with the current
patch set. If
you repost with that fixed, I can put it into scsi-misc and we can
address the other issues later.
I will repost the patch set tommorrow with the following changes
(1) Add readl following writel from the function that disables interrupts
Is a memory barrier required after the writel and before the readl to ensure that
the writel executes before the readl on processors other than x86_64 and ia32?
(2) Replace 0xFFFFFFFFFFFFFFFFULL with ~0ULL
(3) when calling pci_enable_msix, only pass one msix entry (instead of 15).
(4) remove the "current HW implementation uses..... " comment in the sources
(5) merge in a bug fix for SIGIO/POLLIN notifcation reported by the storlib team.
Eric Moore--
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