On Thu, Jan 16, 2025 at 05:11:41PM +0800, Ziqi Chen wrote: You missed CCing linux-arm-msm mailing list to the cover letter. > With OPP V2 enabled, devfreq can scale clocks amongst multiple frequency > plans. However, the gear speed is only toggled between min and max during > clock scaling. Enable multi-level gear scaling by mapping clock frequencies > to gear speeds, so that when devfreq scales clock frequencies we can put > the UFS link at the appropraite gear speeds accordingly. > But the UFSHC PHY settings are not updated for each gear speed, isn't it? Then I'm wondering how much we get out of this 'multi-level gear scaling'. - Mani > This series has been tested on below platforms - > SM8650 + UFS3.1 > SM8750 + UFS4.0 > > > Can Guo (6): > scsi: ufs: core: Pass target_freq to clk_scale_notify() vops > scsi: ufs: qcom: Pass target_freq to clk scale pre and post change > scsi: ufs: core: Add a vops to map clock frequency to gear speed > scsi: ufs: qcom: Implement the freq_to_gear_speed() vops > scsi: ufs: core: Enable multi-level gear scaling > scsi: ufs: core: Toggle Write Booster during clock scaling base on > gear speed > > Ziqi Chen (2): > scsi: ufs: core: Check if scaling up is required when disable clkscale > ARM: dts: msm: Use Operation Points V2 for UFS on SM8650 > > arch/arm64/boot/dts/qcom/sm8650.dtsi | 51 ++++++++++++++++---- > drivers/ufs/core/ufshcd-priv.h | 17 +++++-- > drivers/ufs/core/ufshcd.c | 71 +++++++++++++++++++++------- > drivers/ufs/host/ufs-mediatek.c | 1 + > drivers/ufs/host/ufs-qcom.c | 60 ++++++++++++++++++----- > include/ufs/ufshcd.h | 8 +++- > 6 files changed, 166 insertions(+), 42 deletions(-) > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்
