On 8/22/24 7:57 PM, Peter Wang (王信友) wrote:
You assume that the following steps are executed in sequence. (Theread A) send ufshcd_uic_pwr_ctrl (ISR) UIC_POWER_MODE A clear hab->active_uic_cmd (ISR) UIC_COMMAND_COMPL A (step A) do nothing (Thread B) ufshcd_send_uic_cmd set hab->active_uic_cmd (step B) (ISR) UIC_COMMAND_COMPL B complte thread B's cmd But actually step A ISR may come after step B and cause error. (Theread A) send ufshcd_uic_pwr_ctrl (ISR) UIC_POWER_MODE A clear hab->active_uic_cmd (Thread B) ufshcd_send_uic_cmd set hab->active_uic_cmd (step B) (ISR) UIC_COMMAND_COMPL A (step A) complete Thread A cmd
Hi Peter, Can you please take a look at the fix I proposed in my reply to Bao? Thanks, Bart.
