Hi Peter > -----Original Message----- > From: Peter Griffin <peter.griffin@xxxxxxxxxx> > Sent: Thursday, April 4, 2024 5:56 PM > To: mturquette@xxxxxxxxxxxx; sboyd@xxxxxxxxxx; robh@xxxxxxxxxx; > krzk+dt@xxxxxxxxxx; conor+dt@xxxxxxxxxx; vkoul@xxxxxxxxxx; > kishon@xxxxxxxxxx; alim.akhtar@xxxxxxxxxxx; avri.altman@xxxxxxx; > bvanassche@xxxxxxx; s.nawrocki@xxxxxxxxxxx; cw00.choi@xxxxxxxxxxx; > jejb@xxxxxxxxxxxxx; martin.petersen@xxxxxxxxxx; > chanho61.park@xxxxxxxxxxx; ebiggers@xxxxxxxxxx > Cc: linux-scsi@xxxxxxxxxxxxxxx; linux-phy@xxxxxxxxxxxxxxxxxxx; > devicetree@xxxxxxxxxxxxxxx; linux-clk@xxxxxxxxxxxxxxx; linux-samsung- > soc@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-arm- > kernel@xxxxxxxxxxxxxxxxxxx; tudor.ambarus@xxxxxxxxxx; > andre.draszik@xxxxxxxxxx; saravanak@xxxxxxxxxx; > willmcvicker@xxxxxxxxxx; Peter Griffin <peter.griffin@xxxxxxxxxx> > Subject: [PATCH 00/17] HSI2, UFS & UFS phy support for Tensor GS101 > > Hi folks, > > > Question > ======== > > Currently the link comes up in Gear 3 due to ufshcd_init_host_params() > host_params initialisation. If I update that to use UFS_HS_G4 for negotiation > then the link come up in Gear 4. I propose (in a future patch) to use VER > register offset 0x8 to determine whether to set G4 capability or not (if major > version is >= 3). > > The bitfield of VER register in gs101 docs is > > RSVD [31:16] Reserved > MJR [15:8] Major version number > MNR [7:4] Minor version number > VS [3:0] Version Suffix > > Can anyone confirm if other Exynos platforms supported by this driver have > the same register, and if it conforms to the bitfield described above? > VER (offset 0x8) is standard UFS HCI spec, so all vendor need to have this (unless something really wrong with the HW) Yes, Exynos and FSD SoC has these bitfield implemented. > > 2.44.0.478.gd926399ef9-goog
