Thanks John for your comments here. Will do it in v4. > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > On 08/04/2022 09:05, Ajish Koshy wrote: > > Executing driver on servers with more than 32 CPUs were faced with > > command timeouts. This is because we were not geting completions for > > commands submitted on IQ32 - IQ63. > > > > Set E64Q bit to enable upper inbound and outbound queues 32 to 63 in > > the MPI main configuration table. > > > > Added 500ms delay after successful MPI initialization as mentioned in > > controller datasheet. > > > > Signed-off-by: Ajish Koshy <Ajish.Koshy@xxxxxxxxxxxxx> > > Signed-off-by: Viswas G <Viswas.G@xxxxxxxxxxxxx> > > Fixes: 05c6c029a44d ("scsi: pm80xx: Increase number of supported > > queues") > > Reviewed-by: Damien Le Moal <damien.lemoal@xxxxxxxxxxxxxxxxxx> > > --- > > drivers/scsi/pm8001/pm80xx_hwi.c | 6 ++++++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c > > b/drivers/scsi/pm8001/pm80xx_hwi.c > > index cdb31679f419..71b6cc4b9420 100644 > > --- a/drivers/scsi/pm8001/pm80xx_hwi.c > > +++ b/drivers/scsi/pm8001/pm80xx_hwi.c > > @@ -766,6 +766,10 @@ static void init_default_table_values(struct > pm8001_hba_info *pm8001_ha) > > pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = > 0x01; > > pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01; > > > > + /* Enable higher IQs and OQs, 32 to 63, bit 16 */ > > + if (pm8001_ha->max_q_num > 32) > > + pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |= > > + 1 << 16; > > /* Disable end to end CRC checking */ > > pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16); > > > > @@ -1027,6 +1031,8 @@ static int mpi_init_check(struct > pm8001_hba_info *pm8001_ha) > > if (0x0000 != gst_len_mpistate) > > return -EBUSY; > > > > + msleep(500); > > Personally I think you should mention where this 500ms value comes from > (the datasheet), as it is not arbitrary OK. > > The change looks ok apart from that > > > + > > return 0; > > } > >