> > Suganath, > > I applied this series to 5.3/scsi-queue. > > However, I remain unconvinced of the merits of the config page putback. Why > even bother if a controller reset causes the defaults to be loaded from > NVRAM? > > Also, triggering on X86 for selecting performance mode seems questionable. I > would like to see a follow-on patch that comes up with a better heuristic. Martin - AMD EPYC is not efficient w.r.t QPI transaction. I tested performance on AMD EPYC 7601 Chipset. It has totally 128 logical CPU. Aero/Sea controller support at max 128 MSIx vector. In good case scenario, we will have 1:1 CPU to MSIX mapping. I can get 2.4 M IOPS in this case. Just to simulate performance issue, I reduce controller msix vector to 64. It means cpu to msix mapping is 2:1. Indirectly, I am trying to generate completion which requires completion on remote cpu (via call_function_single_interrupt). In this case, I can get 1.7M IOPS. Same test on Intel architecture provides better result (Negligible performance impact). This patch set maps high iops queues (queues with interrupt coalescing turned on) to local numa node. High iops queue count is limited and it depends upon QPI for io completion. We have enable this feature only for intel arch where we have seen improvement. Not having this feature is not bad, but if we enable this feature we may get negative impact if QPI overhead (like AMD) is high. Kashyap > > -- > Martin K. Petersen Oracle Linux Engineering
