On 14/01/2019 13:18, Marc Gonzalez wrote: > On 14/01/2019 12:57, Marc Gonzalez wrote: > >> On 13/12/2018 15:24, Marc Gonzalez wrote: >> >>> I'm having trouble getting UFS working on an APQ8098 MEDIABOX dev board. >>> (I'm running v4.20-rc4 with a few UFS patches taken off the MSM list.) >>> >>> I'm hoping someone with experience with the UFSHC will spot the one thing >>> missing that will make everything work! >> >> Based on Jeffrey's feedback, I looked at voltage regulators again, and >> I think there might be an issue in drivers/scsi/ufs/ufshcd.c >> >> ufshcd_enable_vreg() is supposed to enable a given voltage regulator. >> >> To do so it calls ufshcd_config_vreg() and then regulator_enable() >> >> ufshcd_config_vreg() calls regulator_set_voltage() and regulator_set_load() >> >> However, regulator_set_load() fails if the regulator is not enabled. >> >> So ufshcd_enable_vreg() fails because the regulator is not enabled... >> >> Catch 22? > > The code was introduced 4 years ago, and has never changed. I'm surprised > no one ever experienced an issue. Perhaps I have misunderstood... I did *indeed* misunderstand the regulator core implementation. Doh! After adding the "regulator-allow-set-load" property to the vreg DT nodes, the UFSHC driver was finally able to talk to the Flash chip! However, all is not well yet :-) First, I had to turn ufshcd_set_vccq_rail_unused() into a NOP, otherwise my board locks up and reboots. I'm not sure how to handle this issue gracefully? Second, the system runs for a while, then locks up and reboots without any warning from the kernel when I read large partitions on the Flash. This is what the boot loader prints after rebooting: Format: Log Type - Time(microsec) - Message - Optional Info Log Type: B - Since Boot(Power On Reset), D - Delta, S - Statistic S - QC_IMAGE_VERSION_STRING=BOOT.XF.1.2.2-00157-M8998LZB-1 S - IMAGE_VARIANT_STRING=Msm8998LA S - OEM_IMAGE_VERSION_STRING=speedcore S - Boot Interface: UFS S - Secure Boot: Off S - Boot Config @ 0x00786070 = 0x000002c1 S - JTAG ID @ 0x00786130 = 0x200620e1 S - OEM ID @ 0x00786138 = 0x00000000 S - Serial Number @ 0x00784138 = 0x13ab5626 S - OEM Config Row 0 @ 0x00784188 = 0x0000000000000000 S - OEM Config Row 1 @ 0x00784190 = 0x0000000000004000 S - Feature Config Row 0 @ 0x007841a0 = 0x0050300000000000 S - Feature Config Row 1 @ 0x007841a8 = 0x0000ffff00087fff S - Core 0 Frequency, 1305 MHz S - PBL Patch Ver: 1 B - 0 - PBL, Start B - 9445 - bootable_media_detect_entry, Start B - 55554 - bootable_media_detect_success, Start B - 55561 - elf_loader_entry, Start B - 56863 - auth_hash_seg_entry, Start B - 57182 - auth_hash_seg_exit, Start B - 107656 - elf_segs_hash_verify_entry, Start B - 139038 - elf_segs_hash_verify_exit, Start B - 139054 - auth_xbl_sec_hash_seg_entry, Start B - 162941 - auth_xbl_sec_hash_seg_exit, Start B - 162943 - xbl_sec_segs_hash_verify_entry, Start B - 168355 - xbl_sec_segs_hash_verify_exit, Start B - 168421 - PBL, End B - 201818 - SBL1, Start B - 323757 - boot_flash_init, Start D - 30 - boot_flash_init, Delta B - 326289 - sbl1_ddr_set_default_params, Start D - 0 - sbl1_ddr_set_default_params, Delta B - 334310 - boot_config_data_table_init, Start D - 130723 - boot_config_data_table_init, Delta - (60 Bytes) B - 469578 - CDT Version:3,Platform ID:8,Major ID:1,Minor ID:0,Subtype:1 B - 474275 - Image Load, Start D - 580 - Auth Metadata D - 549 - Segments hash check D - 12322 - PMIC Image Loaded, Delta - (45640 Bytes) B - 489921 - pm_device_init, Start B - 497455 - PM: PON REASON: PM0=0x4000024000020020:0x40 PM1=0x4000084000080020:0x800 PM2=0x4000084000080020:0x800 B - 556350 - PM: SET_VAL:Skip D - 62738 - pm_device_init, Delta B - 558272 - pm_driver_init, Start D - 5215 - pm_driver_init, Delta B - 566781 - pm_sbl_chg_init, Start B - 569069 - PM: Trigger FG IMA Reset B - 572637 - PM: Trigger FG IMA Reset.Completed B - 578127 - PM: BOOTUP, Debug Board being used D - 11529 - pm_sbl_chg_init, Delta B - 585081 - vsense_init, Start D - 0 - vsense_init, Delta B - 642238 - Pre_DDR_clock_init, Start D - 213 - Pre_DDR_clock_init, Delta D - 0 - sbl1_ddr_set_params, Delta B - 651632 - do_ddr_training, Start D - 0 - do_ddr_training, Delta B - 676764 - clock_init, Start D - 335 - clock_init, Delta B - 679692 - Image Load, Start D - 2074 - APDP Image Loaded, Delta - (0 Bytes) B - 890051 - usb: chgr - SDP_CHARGER B - 890630 - Image Load, Start D - 6496 - Auth Metadata D - 4270 - Segments hash check D - 15952 - XBLRamDump Image Loaded, Delta - (314564 Bytes) I had a look at "[8998] How to check PMIC PON reason" but I'm not sure how to read PM0=0x4000024000020020:0x40 PM1=0x4000084000080020:0x800 PM2=0x4000084000080020:0x800 Regards.
