On Mon, 2005-12-12 at 15:00 -0600, Michael Reed wrote: > (The subject of this email isn't quite accurate. It's not > a pci coherency problem, it's a pio write ordering problem.) > > I've been asked to pass along the suggestion that "mmiowb" > should be implemented for the platform. > Given that I've been unable to unearth the chipset documentation > for the Vis WS, I can only hope that you've got some good ideas > on how this might be accomplished. Well, the idea was that mmiowb and posting flushes were orthogonal. mmiowb would be used in places where a posted write flush was done but was strictly unnnecessary. This bug report is implying that the posted write flush was necessary, so it was incorrectly replaced with mmiowb (which is a nop on most platforms). > I agree that replacing the pio read which flushed the preceeding > pio write with mmiowb() is what has likely broken the driver. If you > restore them, please make it either mmiowb or pio read, but not both. > > Perhaps something like this? It's not the most elegant solution.... I'm tempted to say I think we need to put the write posting flush back in and dump the mmiowb(), but since the driver is supposedly doing PIO for VISWS, there's something else going on here (PIO writes aren't supposed to post). I've cc'd the VISWS maintainer in case he can think of anything. James - : send the line "unsubscribe linux-scsi" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
