Hi Devang > -----Original Message----- > From: Devang Tailor <dev.tailor@xxxxxxxxxxx> > Sent: Wednesday, January 8, 2025 11:20 AM > To: alim.akhtar@xxxxxxxxxxx; dev.tailor@xxxxxxxxxxx; robh@xxxxxxxxxx; > krzk+dt@xxxxxxxxxx; conor+dt@xxxxxxxxxx > Cc: devicetree@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux- > samsung-soc@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; > faraz.ata@xxxxxxxxxxx > Subject: [PATCH v2] arm64: dts: add cpu cache information to ExynosAuto- > v920 > > Add CPU caches information to its dt nodes so that the same is available to > userspace via sysfs. This SoC has 64/64 KB I/D cache and 256KB of L2 cache for > each core, 2 MB of shared L3 cache for each quad cpu cluster and 1 MB of > shared L3 cache for the dual cpu cluster. > > Signed-off-by: Devang Tailor <dev.tailor@xxxxxxxxxxx> > > --- > Changes in v2: > - Added L3 cache for all the three cpu clusters > - Corrected L2 cache numbering as a part of review comments from Krzysztof > and updated as per cpus clusters. > - Link to v1: https://patchwork.kernel.org/project/linux-arm- > kernel/patch/20241231064350.523713-1-dev.tailor@xxxxxxxxxxx/ > --- > .../arm64/boot/dts/exynos/exynosautov920.dtsi | 127 > ++++++++++++++++++ > 1 file changed, 127 insertions(+) > [snip] > + l3_cache_cl0: l3-cache0 { You can add one node for cl0 and cl1, say "l3_cache_cl0_cl1" and Remove the specific node for CL1, because both are same. > + compatible = "cache"; > + cache-level = <3>; > + cache-unified; > + cache-size = <0x200000>;/* 2MB L3 cache for cpu > cluster-0 */ > + cache-line-size = <64>; > + cache-sets = <2048>; > + }; > + > + l3_cache_cl1: l3-cache1 { > + compatible = "cache"; > + cache-level = <3>; > + cache-unified; > + cache-size = <0x200000>;/* 2MB L3 cache for cpu > cluster-1 */ > + cache-line-size = <64>; > + cache-sets = <2048>; > + }; > + [snip] > + l3_cache_cl2: l3-cache2 { > 2.34.1
