On 31/12/2024 07:43, Devang Tailor wrote:
>
> cpu9: cpu@20100 {
> @@ -152,6 +215,22 @@ cpu9: cpu@20100 {
> compatible = "arm,cortex-a78ae";
> reg = <0x0 0x20100>;
> enable-method = "psci";
> + i-cache-size = <0x10000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x10000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&cpu_l2>;
> + };
> +
> + cpu_l2: l2-cache0 {
Are there more l2-caches? '0' suggests that, so please add nodes for all
of them.
Best regards,
Krzysztof
