Hi Alim,
> -----Original Message-----
> From: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
> Sent: Wednesday, November 27, 2024 11:47 AM
> To: 'Sowon Na' <sowon.na@xxxxxxxxxxx>; robh@xxxxxxxxxx; krzk@xxxxxxxxxx;
> conor+dt@xxxxxxxxxx; vkoul@xxxxxxxxxx; kishon@xxxxxxxxxx
> Cc: krzk+dt@xxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; linux-samsung-soc@xxxxxxxxxxxxxxx
> Subject: RE: [PATCH v3 3/3] arm64: dts: exynosautov920: add ufs phy for
> ExynosAutov920 SoC
>
>
>
> > -----Original Message-----
> > From: Sowon Na <sowon.na@xxxxxxxxxxx>
> > Sent: Monday, November 18, 2024 7:40 AM
> > To: robh@xxxxxxxxxx; krzk@xxxxxxxxxx; conor+dt@xxxxxxxxxx;
> > vkoul@xxxxxxxxxx; alim.akhtar@xxxxxxxxxxx; kishon@xxxxxxxxxx
> > Cc: krzk+dt@xxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx;
> > devicetree@xxxxxxxxxxxxxxx; linux-samsung-soc@xxxxxxxxxxxxxxx;
> > sowon.na@xxxxxxxxxxx
> > Subject: [PATCH v3 3/3] arm64: dts: exynosautov920: add ufs phy for
> > ExynosAutov920 SoC
> >
> > Add UFS Phy for ExynosAutov920
> >
> > Like ExynosAutov9, this also uses fixed-rate clock nodes until clock
> > driver has been supported. The clock nodes are initialized on
> > bootloader stage thus we don't need to control them so far.
> >
> > Signed-off-by: Sowon Na <sowon.na@xxxxxxxxxxx>
> > ---
> Reviewed-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
>
> Are you planning to send UFS HCI patches as well?
Yes, I will send UFS HCI patches for ExynosAutov920 after phy patches.
Really thank you for your reviews.
>
> > arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 11 +++++++++++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > index c759134c909e..505ba04722de 100644
> > --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > @@ -361,6 +361,17 @@ pinctrl_aud: pinctrl@1a460000 {
> > compatible = "samsung,exynosautov920-pinctrl";
> > reg = <0x1a460000 0x10000>;
> > };
> > +
> > + ufs_0_phy: phy@16e04000 {
> > + compatible = "samsung,exynosautov920-ufs-phy";
> > + reg = <0x16e04000 0x4000>;
> > + reg-names = "phy-pma";
> > + clocks = <&xtcxo>;
> > + clock-names = "ref_clk";
> > + samsung,pmu-syscon = <&pmu_system_controller>;
> > + #phy-cells = <0>;
> > + status = "disabled";
> > + };
> > };
> >
> > timer {
> > --
> > 2.45.2
>
