Signed-off-by: Kwanghoon Son <k.son@xxxxxxxxxxx>
---
drivers/clk/samsung/clk-exynosautov9.c | 35 ++++++++++++++++++++++++
include/dt-bindings/clock/samsung,exynosautov9.h | 4 +++
2 files changed, 39 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
index 5971e680e566..ea9c02360e7f 100644
--- a/drivers/clk/samsung/clk-exynosautov9.c
+++ b/drivers/clk/samsung/clk-exynosautov9.c
@@ -20,6 +20,7 @@
#define CLKS_NR_TOP (GOUT_CLKCMU_PERIS_BUS + 1)
#define CLKS_NR_BUSMC (CLK_GOUT_BUSMC_SPDMA_PCLK + 1)
#define CLKS_NR_CORE (CLK_GOUT_CORE_CMU_CORE_PCLK + 1)
+#define CLKS_NR_DPTX (CLK_MOUT_DPTX_DPGTC_USER + 1)
#define CLKS_NR_DPUM (CLK_GOUT_DPUM_SYSMMU_D3_CLK + 1)
#define CLKS_NR_FSYS0 (CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK + 1)
#define CLKS_NR_FSYS1 (CLK_GOUT_FSYS1_USB30_1_ACLK + 1)
@@ -1077,6 +1078,37 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
.clk_name = "dout_clkcmu_core_bus",
};
+/* ---- CMU_DPTX ---------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_DPTX (0x18a00000) */
+#define PLL_CON0_MUX_CLKCMU_DPTX_BUS_USER 0x0600
+#define PLL_CON0_MUX_CLKCMU_DPTX_DPGTC_USER 0x0610
+
+static const unsigned long dptx_clk_regs[] __initconst = {
+ PLL_CON0_MUX_CLKCMU_DPTX_BUS_USER,
+ PLL_CON0_MUX_CLKCMU_DPTX_DPGTC_USER
+};
+
+PNAME(mout_dptx_bus_user_p) = { "oscclk", "dout_clkcmu_dptx_bus" };
+PNAME(mout_dptx_dpgtc_user_p) = { "oscclk", "dout_clkcmu_dptx_dpgtc" };
+
+
+static const struct samsung_mux_clock dptx_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_DPTX_BUS_USER, "mout_dptx_bus_user",
+ mout_dptx_bus_user_p, PLL_CON0_MUX_CLKCMU_DPTX_BUS_USER, 4, 1),
+ MUX(CLK_MOUT_DPTX_DPGTC_USER, "mout_dptx_dpgtc_user",
+ mout_dptx_dpgtc_user_p, PLL_CON0_MUX_CLKCMU_DPTX_DPGTC_USER, 4, 1),
+};
+
+static const struct samsung_cmu_info dptx_cmu_info __initconst = {
+ .mux_clks = dptx_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(dptx_mux_clks),
+ .nr_clk_ids = CLKS_NR_DPTX,
+ .clk_regs = dptx_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(dptx_clk_regs),
+ .clk_name = "dout_clkcmu_dptx_bus",
+};
+
/* ---- CMU_DPUM ---------------------------------------------------------- */
/* Register Offset definitions for CMU_DPUM (0x18c00000) */
@@ -2165,6 +2197,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = {
}, {
.compatible = "samsung,exynosautov9-cmu-core",
.data = &core_cmu_info,
+ }, {
+ .compatible = "samsung,exynosautov9-cmu-dptx",
+ .data = &dptx_cmu_info,
}, {
.compatible = "samsung,exynosautov9-cmu-dpum",
.data = &dpum_cmu_info,
diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
index ce8fb8f7d718..8fd81a62c2c9 100644
--- a/include/dt-bindings/clock/samsung,exynosautov9.h
+++ b/include/dt-bindings/clock/samsung,exynosautov9.h
@@ -179,6 +179,10 @@
#define CLK_GOUT_CORE_CCI_PCLK 4
#define CLK_GOUT_CORE_CMU_CORE_PCLK 5
+/* CMU_DPTX */
+#define CLK_MOUT_DPTX_BUS_USER 1
+#define CLK_MOUT_DPTX_DPGTC_USER 2
+
/* CMU_DPUM */
#define CLK_MOUT_DPUM_BUS_USER 1
#define CLK_DOUT_DPUM_BUSP 2
--
2.39.2
