On 19/09/2024 14:39, Inbaraj E wrote: > PLL_CAM_CSI is the parent clock for the ACLK and PCLK in the CMU_CAM_CSI > block. When we gate ACLK or PCLK, the clock framework will subsequently > disables the parent clocks(PLL_CAM_CSI). Disabling PLL_CAM_CSI is causing > system level halt. > > It was observed on FSD SoC, when we gate the ACLK and PCLK during CSI stop > streaming through pm_runtime_put system is getting halted. So marking > PLL_CAM_CSI as critical to prevent disabling. No, please do not send new versions while discussion is going. See my replies in previous version. Also, if this stays, then you miss Cc-stable. Best regards, Krzysztof
