The clkdiv values are incorrect as ideal_clk is in kHz and the clock
rate of vclk is in Hz. Multiply 1000 to ideal_clk to bring it to Hz.
Signed-off-by: Kaustabh Chakraborty <kauschluss@xxxxxxxxxxx>
---
drivers/gpu/drm/exynos/exynos7_drm_decon.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
index 2c4ee87ae6ec..4e4ced50ff15 100644
--- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
@@ -137,7 +137,7 @@ static void decon_ctx_remove(struct decon_context *ctx)
static u32 decon_calc_clkdiv(struct decon_context *ctx,
const struct drm_display_mode *mode)
{
- unsigned long ideal_clk = mode->clock;
+ unsigned long ideal_clk = mode->clock * 1000;
u32 clkdiv;
/* Find the clock divider value that gets us closest to ideal_clk */
--
2.46.1
