Quoting Inbaraj E (2024-09-17 03:10:16)
> PLL_CAM_CSI is the parent clock for the ACLK and PCLK in the CMU_CAM_CSI
> block. When we gate ACLK or PCLK, the clock framework will subsequently
> disables the parent clocks(PLL_CAM_CSI). Disabling PLL_CAM_CSI is causing
> sytem level halt.
>
> It was observed on FSD SoC, when we gate the ACLK and PCLK during CSI stop
> streaming through pm_runtime_put system is getting halted. So marking
> PLL_CAM_CSI as critical to prevent disabling.
>
> Signed-off-by: Inbaraj E <inbaraj.e@xxxxxxxxxxx>
> ---
Please add a fixes tag. Although this is likely a band-aid fix because
marking something critical leaves it enabled forever.
> drivers/clk/samsung/clk-fsd.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-fsd.c b/drivers/clk/samsung/clk-fsd.c
> index 6f984cfcd33c..b1764aab9429 100644
> --- a/drivers/clk/samsung/clk-fsd.c
> +++ b/drivers/clk/samsung/clk-fsd.c
> @@ -1637,8 +1637,9 @@ static const struct samsung_pll_rate_table pll_cam_csi_rate_table[] __initconst
> };
>
> static const struct samsung_pll_clock cam_csi_pll_clks[] __initconst = {
> - PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll",
> - PLL_LOCKTIME_PLL_CAM_CSI, PLL_CON0_PLL_CAM_CSI, pll_cam_csi_rate_table),
> + __PLL(pll_142xx, 0, "fout_pll_cam_csi", "fin_pll",
> + CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL, PLL_LOCKTIME_PLL_CAM_CSI,
Please add a comment indicating that this clk can never turn off because
<insert reason here>.
