On Tue, 06 Aug 2024 14:11:48 +0200, David Virag wrote:
> In Exynos7885 (and seemingly all modern Exynos SoCs) all PLLs have a MUX
> attached to them controlled by bit 4 in the PLL's CON0 register.
>
> These MUXes can select between OSCCLK or the PLL's output, essentially
> making the PLL bypassable.
>
> These weren't modeled in the driver because the vendor provided drivers
> didn't model it properly, instead setting them when updating the PMS
> values.
>
> [...]
Applied, thanks!
[5/7] clk: samsung: exynos7885: Add missing MUX clocks from PLLs in CMU_TOP
https://git.kernel.org/krzk/linux/c/cc9e3e375f4f2e244695040aa416d16ef6d26ddd
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
