On 06/26/2024, Peter Griffin wrote:
> Not all registers in PMU_ALIVE block support atomic set/clear operations.
> GS101_SYSIP_DAT0 and GS101_SYSTEM_CONFIGURATION registers are two regs
> where attempting atomic access fails.
>
> As documentation on exactly which registers support atomic operations is
> not forthcoming. We default to atomic access, unless the register is
> explicitly added to the tensor_is_atomic() function. Update the comment
> to reflect this as well.
>
> Signed-off-by: Peter Griffin <peter.griffin@xxxxxxxxxx>
Reviewed-by: Will McVicker <willmcvicker@xxxxxxxxxx>
Tested-by: Will McVicker <willmcvicker@xxxxxxxxxx>
I verified reboot and power off on my Pixel 6 Pro.
> ---
> drivers/soc/samsung/exynos-pmu.c | 16 ++++++++++++++--
> include/linux/soc/samsung/exynos-regs-pmu.h | 4 ++++
> 2 files changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c
> index 624324f4001c..5556acc7c092 100644
> --- a/drivers/soc/samsung/exynos-pmu.c
> +++ b/drivers/soc/samsung/exynos-pmu.c
> @@ -129,14 +129,26 @@ static int tensor_set_bits_atomic(void *ctx, unsigned int offset, u32 val,
> return ret;
> }
>
> +static bool tensor_is_atomic(unsigned int reg)
> +{
> + switch (reg) {
> + case GS101_SYSIP_DAT0:
> + case GS101_SYSTEM_CONFIGURATION:
> + return false;
> + default:
> + return true;
> + }
> +}
> +
> static int tensor_sec_update_bits(void *ctx, unsigned int reg,
> unsigned int mask, unsigned int val)
> {
> /*
> * Use atomic operations for PMU_ALIVE registers (offset 0~0x3FFF)
> - * as the target registers can be accessed by multiple masters.
> + * as the target registers can be accessed by multiple masters. Some
> + * SFRs don't support this however as reported by tensor_is_atomic()
> */
> - if (reg > PMUALIVE_MASK)
> + if (reg > PMUALIVE_MASK || !tensor_is_atomic(reg))
nit: Should we just move all the logic, e.g. `reg > PMUALIVE_MASK` into `tensor_is_atomic()`?
[...]
Thanks,
Will
