Enable the ufs controller, ufs phy and ufs regulator in device tree.
Signed-off-by: Peter Griffin <peter.griffin@xxxxxxxxxx>
---
.../boot/dts/exynos/google/gs101-oriole.dts | 18 ++++++++++
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 36 +++++++++++++++++++
2 files changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
index 6be15e990b65..fb32f6ce2a4d 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
+++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
@@ -53,6 +53,15 @@ button-power {
wakeup-source;
};
};
+
+ /* TODO: Remove this once S2MPG11 slave PMIC is implemented */
+ ufs_0_fixed_vcc_reg: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "ufs-vcc";
+ gpio = <&gpp0 1 GPIO_ACTIVE_HIGH>;
+ regulator-boot-on;
+ enable-active-high;
+ };
};
&ext_24_5m {
@@ -106,6 +115,15 @@ &serial_0 {
status = "okay";
};
+&ufs_0 {
+ status = "okay";
+ vcc-supply = <&ufs_0_fixed_vcc_reg>;
+};
+
+&ufs_0_phy {
+ status = "okay";
+};
+
&usi_uart {
samsung,clkreq-on; /* needed for UART mode */
status = "okay";
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index 09044deede63..baf630b13154 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -1277,6 +1277,42 @@ pinctrl_hsi2: pinctrl@14440000 {
interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
};
+ ufs_0_phy: phy@17e04000 {
+ compatible = "google,gs101-ufs-phy";
+ reg = <0x14704000 0x3000>;
+ reg-names = "phy-pma";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <0>;
+ clocks = <&ext_24_5m>;
+ clock-names = "ref_clk";
+ status = "disabled";
+ };
+
+ ufs_0: ufs@14700000 {
+ compatible = "google,gs101-ufs";
+ reg = <0x14700000 0x200>,
+ <0x14701100 0x200>,
+ <0x14780000 0xa000>,
+ <0x14600000 0x100>;
+ reg-names = "hci", "vs_hci", "unipro", "ufsp";
+ interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_ACLK>,
+ <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO>,
+ <&cmu_hsi2 CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK>,
+ <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK>,
+ <&cmu_hsi2 CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK>,
+ <&cmu_hsi2 CLK_GOUT_HSI2_SYSREG_HSI2_PCLK>;
+ clock-names = "core_clk", "sclk_unipro_main", "fmp",
+ "ufs_aclk", "ufs_pclk", "sysreg";
+ freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
+ phys = <&ufs_0_phy>;
+ phy-names = "ufs-phy";
+ samsung,sysreg = <&sysreg_hsi2 0x710>;
+ status = "disabled";
+ };
+
cmu_apm: clock-controller@17400000 {
compatible = "google,gs101-cmu-apm";
reg = <0x17400000 0x8000>;
--
2.44.0.769.g3c40516874-goog
