On 04/04/2024 14:25, Peter Griffin wrote: > Add a dedicated compatible and drv_data with associated > hooks for gs101 SoC found on Pixel 6. > > Note we make use of the previously added EXYNOS_UFS_OPT_UFSPR_SECURE > option, to skip initialisation of UFSPR registers as these are only > accessible via SMC call. > > EXYNOS_UFS_OPT_TIMER_TICK_SELECT option is also set to select tick > source. This has been done so as not to effect any existing platforms. > > DBG_OPTION_SUITE on gs101 has different address offsets to other SoCs > so these register offsets now come from uic_attr struct. > > Signed-off-by: Peter Griffin <peter.griffin@xxxxxxxxxx> > --- Acked-by: Krzysztof Kozlowski <krzk@xxxxxxxxxx> Best regards, Krzysztof
