Define CPU cluster 0 and CPU cluster 1 CMUs, which generate CPU clocks,
and add corresponding CPU clocks to CPU nodes.
Signed-off-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
---
arch/arm64/boot/dts/exynos/exynos850.dtsi | 26 +++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi
index 2ba67c3d0681..0706c8534ceb 100644
--- a/arch/arm64/boot/dts/exynos/exynos850.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi
@@ -93,6 +93,8 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0x0>;
enable-method = "psci";
+ clocks = <&cmu_cpucl0 CLK_CLUSTER0_SCLK>;
+ clock-names = "cluster0_clk";
};
cpu1: cpu@1 {
device_type = "cpu";
@@ -117,6 +119,8 @@ cpu4: cpu@100 {
compatible = "arm,cortex-a55";
reg = <0x100>;
enable-method = "psci";
+ clocks = <&cmu_cpucl1 CLK_CLUSTER1_SCLK>;
+ clock-names = "cluster1_clk";
};
cpu5: cpu@101 {
device_type = "cpu";
@@ -254,6 +258,28 @@ cmu_peri: clock-controller@10030000 {
"dout_peri_uart", "dout_peri_ip";
};
+ cmu_cpucl1: clock-controller@10800000 {
+ compatible = "samsung,exynos850-cmu-cpucl1";
+ reg = <0x10800000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL1_SWITCH>,
+ <&cmu_top CLK_DOUT_CPUCL1_DBG>;
+ clock-names = "oscclk", "dout_cpucl1_switch",
+ "dout_cpucl1_dbg";
+ };
+
+ cmu_cpucl0: clock-controller@10900000 {
+ compatible = "samsung,exynos850-cmu-cpucl0";
+ reg = <0x10900000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>, <&cmu_top CLK_DOUT_CPUCL0_SWITCH>,
+ <&cmu_top CLK_DOUT_CPUCL0_DBG>;
+ clock-names = "oscclk", "dout_cpucl0_switch",
+ "dout_cpucl0_dbg";
+ };
+
cmu_g3d: clock-controller@11400000 {
compatible = "samsung,exynos850-cmu-g3d";
reg = <0x11400000 0x8000>;
--
2.39.2
