On Tue, Feb 6, 2024 at 2:52 AM Tudor Ambarus <tudor.ambarus@xxxxxxxxxx> wrote:
>
> Add support for GS101 SPI. GS101 integrates 16 SPI nodes, all with 64
> bytes FIFOs. GS101 allows just 32 bit register accesses, otherwise a
> Serror Interrupt is raised. Do the write reg accesses in 32 bits.
>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@xxxxxxxxxx>
> ---
Reviewed-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
> drivers/spi/spi-s3c64xx.c | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> index cb45ad615f3d..9ad0d513fb30 100644
> --- a/drivers/spi/spi-s3c64xx.c
> +++ b/drivers/spi/spi-s3c64xx.c
> @@ -19,7 +19,7 @@
> #include <linux/spi/spi.h>
> #include <linux/types.h>
>
> -#define MAX_SPI_PORTS 12
> +#define MAX_SPI_PORTS 16
> #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
> #define AUTOSUSPEND_TIMEOUT 2000
>
> @@ -1538,6 +1538,19 @@ static const struct s3c64xx_spi_port_config fsd_spi_port_config = {
> .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
> };
>
> +static const struct s3c64xx_spi_port_config gs101_spi_port_config = {
> + .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f,
> + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f},
> + .rx_lvl_offset = 15,
> + .tx_st_done = 25,
> + .clk_div = 4,
> + .high_speed = true,
> + .clk_from_cmu = true,
> + .has_loopback = true,
> + .use_32bit_io = true,
> + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
> +};
> +
> static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
> {
> .name = "s3c2443-spi",
> @@ -1550,6 +1563,9 @@ static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
> };
>
> static const struct of_device_id s3c64xx_spi_dt_match[] = {
> + { .compatible = "google,gs101-spi",
> + .data = &gs101_spi_port_config,
> + },
> { .compatible = "samsung,s3c2443-spi",
> .data = &s3c2443_spi_port_config,
> },
> --
> 2.43.0.594.gd9cf4e227d-goog
>
