Hello Shradha
> -----Original Message-----
> From: Shradha Todi <shradha.t@xxxxxxxxxxx>
> Sent: Wednesday, January 24, 2024 4:09 PM
> To: linux-clk@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-
> pci@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux-samsung-
> soc@xxxxxxxxxxxxxxx
> Cc: mturquette@xxxxxxxxxxxx; sboyd@xxxxxxxxxx; jingoohan1@xxxxxxxxx;
> lpieralisi@xxxxxxxxxx; kw@xxxxxxxxx; robh@xxxxxxxxxx;
> bhelgaas@xxxxxxxxxx; krzysztof.kozlowski@xxxxxxxxxx;
> alim.akhtar@xxxxxxxxxxx; linux@xxxxxxxxxxxxxxx;
> m.szyprowski@xxxxxxxxxxx; manivannan.sadhasivam@xxxxxxxxxx;
> pankaj.dubey@xxxxxxxxxxx; Shradha Todi <shradha.t@xxxxxxxxxxx>
> Subject: [PATCH v4 2/2] PCI: exynos: Adapt to clk_bulk_* APIs
>
> There is no need to hardcode the clock info in the driver as driver can rely on
> the devicetree to supply the clocks required for the functioning of the
> peripheral. Get rid of the static clock info and obtain the platform supplied
> clocks. All the clocks supplied is obtained and enabled using the
> devm_clk_bulk_get_all_enable() API.
>
> Signed-off-by: Shradha Todi <shradha.t@xxxxxxxxxxx>
> ---
Reviewed-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
> drivers/pci/controller/dwc/pci-exynos.c | 54 ++-----------------------
> 1 file changed, 4 insertions(+), 50 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-exynos.c
> b/drivers/pci/controller/dwc/pci-exynos.c
> index ec5611005566..3234eb5be1fb 100644
> --- a/drivers/pci/controller/dwc/pci-exynos.c
> +++ b/drivers/pci/controller/dwc/pci-exynos.c
> @@ -54,43 +54,11 @@
> struct exynos_pcie {
> struct dw_pcie pci;
> void __iomem *elbi_base;
> - struct clk *clk;
> - struct clk *bus_clk;
> + struct clk_bulk_data *clks;
> struct phy *phy;
> struct regulator_bulk_data supplies[2];
> };
>
> -static int exynos_pcie_init_clk_resources(struct exynos_pcie *ep) -{
> - struct device *dev = ep->pci.dev;
> - int ret;
> -
> - ret = clk_prepare_enable(ep->clk);
> - if (ret) {
> - dev_err(dev, "cannot enable pcie rc clock");
> - return ret;
> - }
> -
> - ret = clk_prepare_enable(ep->bus_clk);
> - if (ret) {
> - dev_err(dev, "cannot enable pcie bus clock");
> - goto err_bus_clk;
> - }
> -
> - return 0;
> -
> -err_bus_clk:
> - clk_disable_unprepare(ep->clk);
> -
> - return ret;
> -}
> -
> -static void exynos_pcie_deinit_clk_resources(struct exynos_pcie *ep) -{
> - clk_disable_unprepare(ep->bus_clk);
> - clk_disable_unprepare(ep->clk);
> -}
> -
> static void exynos_pcie_writel(void __iomem *base, u32 val, u32 reg) {
> writel(val, base + reg);
> @@ -332,17 +300,9 @@ static int exynos_pcie_probe(struct platform_device
> *pdev)
> if (IS_ERR(ep->elbi_base))
> return PTR_ERR(ep->elbi_base);
>
> - ep->clk = devm_clk_get(dev, "pcie");
> - if (IS_ERR(ep->clk)) {
> - dev_err(dev, "Failed to get pcie rc clock\n");
> - return PTR_ERR(ep->clk);
> - }
> -
> - ep->bus_clk = devm_clk_get(dev, "pcie_bus");
> - if (IS_ERR(ep->bus_clk)) {
> - dev_err(dev, "Failed to get pcie bus clock\n");
> - return PTR_ERR(ep->bus_clk);
> - }
> + ret = devm_clk_bulk_get_all_enable(dev, &ep->clks);
> + if (ret < 0)
> + return ret;
>
> ep->supplies[0].supply = "vdd18";
> ep->supplies[1].supply = "vdd10";
> @@ -351,10 +311,6 @@ static int exynos_pcie_probe(struct platform_device
> *pdev)
> if (ret)
> return ret;
>
> - ret = exynos_pcie_init_clk_resources(ep);
> - if (ret)
> - return ret;
> -
> ret = regulator_bulk_enable(ARRAY_SIZE(ep->supplies), ep-
> >supplies);
> if (ret)
> return ret;
> @@ -369,7 +325,6 @@ static int exynos_pcie_probe(struct platform_device
> *pdev)
>
> fail_probe:
> phy_exit(ep->phy);
> - exynos_pcie_deinit_clk_resources(ep);
> regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
>
> return ret;
> @@ -383,7 +338,6 @@ static int __exit exynos_pcie_remove(struct
> platform_device *pdev)
> exynos_pcie_assert_core_reset(ep);
> phy_power_off(ep->phy);
> phy_exit(ep->phy);
> - exynos_pcie_deinit_clk_resources(ep);
> regulator_bulk_disable(ARRAY_SIZE(ep->supplies), ep->supplies);
>
> return 0;
> --
> 2.17.1
