On Mon, Jan 22, 2024 at 4:57 PM Peter Griffin <peter.griffin@xxxxxxxxxx> wrote:
>
> Newer Exynos SoCs have atomic set/clear bit hardware for PMU registers as
> these registers can be accessed by multiple masters. Some platforms also
> protect the PMU registers for security hardening reasons so they can't be
> written by normal world and are only write acessible in el3 via a SMC call.
>
> Add support for both of these usecases using SoC specific quirks that are
> determined from the DT compatible string.
>
> Drivers which need to read and write PMU registers should now use these
> new exynos_pmu_*() APIs instead of obtaining a regmap using
> syscon_regmap_lookup_by_phandle()
>
> Depending on the SoC specific quirks, the exynos_pmu_*() APIs will access
> the PMU register in the appropriate way.
>
> Signed-off-by: Peter Griffin <peter.griffin@xxxxxxxxxx>
> ---
> drivers/soc/samsung/exynos-pmu.c | 209 ++++++++++++++++++++++++-
> drivers/soc/samsung/exynos-pmu.h | 4 +
> include/linux/soc/samsung/exynos-pmu.h | 28 ++++
> 3 files changed, 234 insertions(+), 7 deletions(-)
>
[snip]
> +
> +int exynos_pmu_update_bits(unsigned int offset, unsigned int mask,
> + unsigned int val)
> +{
> + if (pmu_context->pmu_data &&
> + pmu_context->pmu_data->quirks & QUIRK_PMU_ALIVE_WRITE_SEC)
> + return rmw_priv_reg(pmu_context->pmu_base_pa + offset,
> + mask, val);
> +
> + return regmap_update_bits(pmu_context->pmureg, offset, mask, val);
> +}
> +EXPORT_SYMBOL(exynos_pmu_update_bits);
> +
This seems a bit hacky, from the design perspective. This way the user
will have to worry about things like driver dependencies, making sure
everything is instantiated in a correct order, etc. It also hides the
details otherwise visible through "syscon-phandle" property in the
device tree. Can we instead rework it by overriding regmap
implementation for Exynos specifics, and then continue to use it in
the leaf drivers via "syscon-phandle" property?
[snip]
