This series enables SPI for Exynos850 SoC. The summary:
1. Enable PDMA, it's needed for SPI (dts, clk)
2. Propagate SPI src clock rate change up to DIV clocks, to make it
possible to change SPI frequency (clk driver)
3. Add Exynos850 support in SPI driver
4. Add SPI nodes to Exynos850 SoC dtsi
All SPI instances were tested using `spidev_test' tool in all 3 possible
modes:
- Polling mode: xfer_size <= 32
- IRQ mode: 64 >= xfer_size >= 32
- DMA mode: xfer_size > 64
with 200 kHz ... 49.9 MHz SPI frequencies. The next 3 approaches were
used:
1. Software loopback ('-l' option for `spidev_test' tool)
2. Hardware loopback (by connecting MISO line to MOSI)
3. By communicating with ATMega found on Sensors Mezzanine board [1],
programmed to act as an SPI slave device
and all the transactions were additionally checked on my Logic Analyzer
to make sure the SCK frequencies were actually correct.
[1] https://www.96boards.org/product/sensors-mezzanine/
Sam Protsenko (7):
dt-bindings: clock: exynos850: Add PDMA clocks
dt-bindings: spi: samsung: Add Exynos850 SPI
clk: samsung: exynos850: Add PDMA clocks
clk: samsung: exynos850: Propagate SPI IPCLK rate change
spi: s3c64xx: Add Exynos850 support
arm64: dts: exynos: Add PDMA node for Exynos850
arm64: dts: exynos: Add SPI nodes for Exynos850
.../devicetree/bindings/spi/samsung,spi.yaml | 1 +
arch/arm64/boot/dts/exynos/exynos850.dtsi | 64 +++++++++++++++++++
drivers/clk/samsung/clk-exynos850.c | 42 +++++++-----
drivers/spi/spi-s3c64xx.c | 14 ++++
include/dt-bindings/clock/exynos850.h | 2 +
5 files changed, 106 insertions(+), 17 deletions(-)
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2.39.2
