On Tue, Jan 9, 2024 at 7:00 AM Tudor Ambarus <tudor.ambarus@xxxxxxxxxx> wrote:
>
> GS101's Connectivity Peripheral blocks (peric0/1 blocks) which
> include the I3C and USI (I2C, SPI, UART) only allow 32-bit
> register accesses.
>
> Instead of specifying the reg-io-width = 4 everywhere, for each node,
> the requirement should be deduced from the compatible.
>
> Infer UPIO_MEM32 iotype from the "google,gs101-uart" compatible.
> Update the uart info name to be GS101 specific in order to
> differentiate from the other exynos platforms. All the other settings
> are not changed.
>
> exynos_fifoszdt_serial_drv_data was replaced by gs101_serial_drv_data
> because the iotype restriction is gs101 specific and there was no other
> user of exynos_fifoszdt_serial_drv_data.
>
> Reviewed-by: Peter Griffin <peter.griffin@xxxxxxxxxx>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@xxxxxxxxxx>
> ---
Reviewed-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
> v3: collect Peter's R-b tag
> v2: new patch
>
> drivers/tty/serial/samsung_tty.c | 38 +++++++++++++++++++++++---------
> 1 file changed, 28 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
> index ff646cddd3f8..a81b61953a28 100644
> --- a/drivers/tty/serial/samsung_tty.c
> +++ b/drivers/tty/serial/samsung_tty.c
> @@ -2497,25 +2497,43 @@ static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
> .fifosize = { 256, 64, 64, 64 },
> };
>
> -/*
> - * Common drv_data struct for platforms that specify samsung,uart-fifosize in
> - * device tree.
> - */
> -static const struct s3c24xx_serial_drv_data exynos_fifoszdt_serial_drv_data = {
> - EXYNOS_COMMON_SERIAL_DRV_DATA(),
> +static const struct s3c24xx_serial_drv_data gs101_serial_drv_data = {
> + .info = {
> + .name = "Google GS101 UART",
> + .type = TYPE_S3C6400,
> + .port_type = PORT_S3C6400,
> + .iotype = UPIO_MEM32,
> + .has_divslot = 1,
> + .rx_fifomask = S5PV210_UFSTAT_RXMASK,
> + .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
> + .rx_fifofull = S5PV210_UFSTAT_RXFULL,
> + .tx_fifofull = S5PV210_UFSTAT_TXFULL,
> + .tx_fifomask = S5PV210_UFSTAT_TXMASK,
> + .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
> + .def_clk_sel = S3C2410_UCON_CLKSEL0,
> + .num_clks = 1,
> + .clksel_mask = 0,
> + .clksel_shift = 0,
> + },
> + .def_cfg = {
> + .ucon = S5PV210_UCON_DEFAULT,
> + .ufcon = S5PV210_UFCON_DEFAULT,
> + .has_fracval = 1,
> + },
> + /* samsung,uart-fifosize must be specified in the device tree. */
> .fifosize = { 0 },
> };
>
> #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
> #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
> #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
> -#define EXYNOS_FIFOSZDT_DRV_DATA (&exynos_fifoszdt_serial_drv_data)
> +#define GS101_SERIAL_DRV_DATA (&gs101_serial_drv_data)
>
> #else
> #define EXYNOS4210_SERIAL_DRV_DATA NULL
> #define EXYNOS5433_SERIAL_DRV_DATA NULL
> #define EXYNOS850_SERIAL_DRV_DATA NULL
> -#define EXYNOS_FIFOSZDT_DRV_DATA NULL
> +#define GS101_SERIAL_DRV_DATA NULL
> #endif
>
> #ifdef CONFIG_ARCH_APPLE
> @@ -2603,7 +2621,7 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
> .driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
> }, {
> .name = "gs101-uart",
> - .driver_data = (kernel_ulong_t)EXYNOS_FIFOSZDT_DRV_DATA,
> + .driver_data = (kernel_ulong_t)GS101_SERIAL_DRV_DATA,
> },
> { },
> };
> @@ -2626,7 +2644,7 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = {
> { .compatible = "axis,artpec8-uart",
> .data = ARTPEC8_SERIAL_DRV_DATA },
> { .compatible = "google,gs101-uart",
> - .data = EXYNOS_FIFOSZDT_DRV_DATA },
> + .data = GS101_SERIAL_DRV_DATA },
> {},
> };
> MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
> --
> 2.43.0.472.g3155946c3a-goog
>
>
