Hi Tudor, On Thu, 28 Dec 2023 at 12:58, Tudor Ambarus <tudor.ambarus@xxxxxxxxxx> wrote: > > GS101's Connectivity Peripheral blocks (peric0/1 blocks) which > include the I3C and USI (I2C, SPI, UART) only allow 32-bit > register accesses. > > Instead of specifying the reg-io-width = 4 everywhere, for each node, > the requirement should be deduced from the compatible. > > Infer UPIO_MEM32 iotype from the "google,gs101-uart" compatible. > Update the uart info name to be GS101 specific in order to > differentiate from the other exynos platforms. All the other settings > are not changed. > > exynos_fifoszdt_serial_drv_data was replaced by gs101_serial_drv_data > because the iotype restriction is gs101 specific and there was no other > user of exynos_fifoszdt_serial_drv_data. > > Signed-off-by: Tudor Ambarus <tudor.ambarus@xxxxxxxxxx> Reviewed-by: Peter Griffin <peter.griffin@xxxxxxxxxx>
