On Mon, Sep 12, 2022 at 10:59:43AM +0200, Camel Guo wrote: > Previously the duty cycle was divided equally into h_scl_l, t_scl_h. > This makes the low period of the SCL clock in Fast Mode is only 1.25us > which is way lower than the minimal value (1.3) specified in i2c > specification. In order to make sure t_scl_l, t_scl_h always fullfill > i2c specification, this commit calculates t_scl_l using this formula: > > t_scl_l = clk_cycle * > ((t_low_min + (scl_clock - t_low_min - t_high_min) / 2) / scl_clock) > > where: > t_low_min is the minimal value of low period of the SCL clock in us; > t_high_min is the minimal value of high period of the SCL clock in us; > scl_clock is converted from SCL clock frequency into us. > > Signed-off-by: Camel Guo <camel.guo@xxxxxxxx> Applied to for-next, thanks!
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