On 19/08/2023 05:17, Sam Protsenko wrote: > Modern Exynos chips (like Exynos850) might have 26 MHz OSCCLK external > clock, which is also used as a PHY reference clock. For some USB PHY > controllers (e.g USB DRD PHY block on Exynos850) there is no need to set > the refclk frequency at all (and corresponding bits in CLKRSTCTRL[7:5] > are marked RESERVED), so that value won't be set in the driver. But > even in that case, 26 MHz support still has to be added, otherwise > exynos5_rate_to_clk() fails, which leads in turn to probe error. > > Add the correct value for 26MHz refclk to make it possible to add > support for new Exynos USB DRD PHY controllers. > > Signed-off-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx> > --- Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
