> Subject: [PATCH 3/6] clk: samsung: clk-pll: Implement pll0818x PLL type
>
> pll0818x PLL is used in Exynos850 SoC for CMU_G3D PLL. Operation-wise,
> pll0818x is the same as pll0822x. The only difference is:
> - pl0822x is integer PLL with Middle FVCO (950 to 2400 MHz)
> - pl0818x is integer PLL with Low FVCO (600 to 1200 MHz)
>
> Add pll0818x type as an alias to pll0822x.
>
> Signed-off-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
Reviewed-by: Chanho Park <chanho61.park@xxxxxxxxxxx>
> ---
> drivers/clk/samsung/clk-pll.c | 1 +
> drivers/clk/samsung/clk-pll.h | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
> index 5ceac4c25c1c..74934c6182ce 100644
> --- a/drivers/clk/samsung/clk-pll.c
> +++ b/drivers/clk/samsung/clk-pll.c
> @@ -1314,6 +1314,7 @@ static void __init _samsung_clk_register_pll(struct
> samsung_clk_provider *ctx,
> init.ops = &samsung_pll35xx_clk_ops;
> break;
> case pll_1417x:
> + case pll_0818x:
> case pll_0822x:
> pll->enable_offs = PLL0822X_ENABLE_SHIFT;
> pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; diff --git
> a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index
> 5d5a58d40e7e..0725d485c6ee 100644
> --- a/drivers/clk/samsung/clk-pll.h
> +++ b/drivers/clk/samsung/clk-pll.h
> @@ -34,6 +34,7 @@ enum samsung_pll_type {
> pll_1451x,
> pll_1452x,
> pll_1460x,
> + pll_0818x,
> pll_0822x,
> pll_0831x,
> pll_142xx,
> --
> 2.39.1
