On 26/01/2023 10:47, Marek Szyprowski wrote:
> Hi Krzysztof,
>
> On 25.01.2023 10:45, Krzysztof Kozlowski wrote:
>> The soc node is supposed to have only device nodes with MMIO addresses,
>> as reported by dtc W=1:
>>
>> arch/arm/boot/dts/exynos5420.dtsi:1070.24-1075.5:
>> Warning (simple_bus_reg): /soc/bus-wcore: missing or empty reg/ranges property
>>
>> and dtbs_check:
>>
>> exynos5420-arndale-octa.dtb: soc: bus-wcore:
>> {'compatible': ['samsung,exynos-bus'], 'clocks': [[2, 769]], 'clock-names': ['bus'], 'status': ['disabled']} should not be valid under {'type': 'object'}
>>
>> Move the bus nodes and their OPP tables out of SoC to fix this.
>> Re-order them alphabetically while moving and put some of the OPP tables
>> in device nodes (if they are not shared).
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
>
> Frankly speaking I'm not very keen on moving those bus nodes out of
> /soc. Technically speaking this is definitely a part of soc and doesn't
> make much sense outside of it. IMHO they describe SoC hardware details
> and they might be moved somehow under clock controller device(s),
> although this would require some changes in the bindings and drivers.
That's the only way to fix it without change of drivers any ABI
compatibility issue. The same we do for Qualcomm interconnects, e.g.
arch/arm64/boot/dts/qcom/sm8450.dtsi where some interconnects have some
do not have MMIO space.
I want to achieve finally clean dtbs_check run for all Exynos sources.
The in-tree bindings already pass, so now I am fixing the ones coming
from dtschema (simple-bus.yaml in particular).
If you have any other idea how to seamlessly clean it up, I am happy to
hear. But I guess the main problem is that no one is being paid for
doing anything for Samsung Exynos, so for free not many put much effort
into working on it.
Best regards,
Krzysztof
