Hi Marek, Am Sonntag, 18. Dezember 2022, 00:55:57 CET schrieb Marek Vasut: > On 12/16/22 14:25, Alexander Stein wrote: > Hi, > > [...] > > > Oh, nice, thanks for the pointer. When setting > > > >> samsung,burst-clock-frequency = <668250000>; > > > > in imx8mm.dtsi > > I get a non-flickering display using 4 lanes. Although admittedly this is > > just random guessing. I'm not sure which clock exactly has to be in the > > range CHA_DSI_CLK_RANGE is configured to. With 4 lanes SN65DSI84 is > > configured for> > > 205-210 MHz (0x29), while I get these PLL PMS settings on DSIM: > >> samsung-dsim 32e10000.dsi: PLL freq 668250000, (p 4, m 99, s 0) > >> samsung-dsim 32e10000.dsi: hs_clk = 668250000, byte_clk = 83531250, > >> esc_clk > > > > = 16706250 > > If I recall it right, minimum PLL frequency is: > > fPMS=1.2*width*height*bpp*fps=1.2*800*480*24*60=663.5 MHz > > the link frequency is then > > fHS=fPMS/lanes/2=82.9 MHz (on the DDR clock lane) Mh, there is something bogus about this. Right now the PLL freq is set depending on 'samsung,burst-clock-frequency' property. But this actually is somehow depending on the number of lanes I configure. From the debug output hs_clk and PLL freq are identical. AFAICS there is also no divider from PLL to hs_clk in the register map. > So DSI83 should be in the range of 80..85 MHz input clock if I calculate > this right. Can you check what is the value of mode->clock, the > mipi_dsi_panel_format_to_bpp() return value, ctx->dsi->lanes in dsi83 > sm65dsi83_get_dsi_range() ? A working setup on a tianma,tm070jvhg33 display (1280x800) is: > samsung-dsim 32e10000.dsi: PLL freq 891000000, (p 3, m 99, s 0) > samsung-dsim 32e10000.dsi: hs_clk = 891000000, byte_clk = 111375000, esc_clk = 18562500 > sn65dsi83 2-002d: mode->clock: 68200 > sn65dsi83 2-002d: mode bpp: 24 > sn65dsi83 2-002d: ctx->dsi->lanes: 3 > sn65dsi83 2-002d: samsung_dsim_set_pll: 0x37 Calculating backwards, sn64dsi83 is expecting a clock in the range of 275-280 MHz. But I fail to see a corresponding clock in the DSIM PLL configuration. Best regards, Alexander > > AFAICS DSIM bridge is configurung hs_clk, byte_clk and esc_clk just from > > DT > > properties, while SN65DSI84 is using display mode and number of lanes. > > > > Is it expected that the DSIM PLL frequencies are set in DT for a specific > > bridge/display setup? > > No, there should be negotiation between the host and bridge/panel, I > tried to propose two variants, but they were all rejected.
