> -----Original Message----- > From: Mark Brown [mailto:broonie@xxxxxxxxxx] > Sent: 21 October 2022 05:24 PM > To: Padmanabhan Rajanbabu <p.rajanbabu@xxxxxxxxxxx> > Cc: lgirdwood@xxxxxxxxx; robh+dt@xxxxxxxxxx; > krzysztof.kozlowski+dt@xxxxxxxxxx; s.nawrocki@xxxxxxxxxxx; > perex@xxxxxxxx; tiwai@xxxxxxxx; pankaj.dubey@xxxxxxxxxxx; > alim.akhtar@xxxxxxxxxxx; rcsekar@xxxxxxxxxxx; > aswani.reddy@xxxxxxxxxxx; alsa-devel@xxxxxxxxxxxxxxxx; > devicetree@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; linux-samsung- > soc@xxxxxxxxxxxxxxx > Subject: Re: [PATCH 2/6] ASoC: samsung: i2s: configure PSR from sound card > > On Fri, Oct 21, 2022 at 01:30:25PM +0530, Padmanabhan Rajanbabu wrote: > > > We can overcome this scenario to an extent if we can get a flexibility > > to Configure both PSR as well as RFS. > > Why does it make sense for the machine driver to worry about this rather > than having the I2S controller driver configure the clock tree? ____________________________________________ _____ | __ | | | | | \ | |CMU| | | \ | |FSD |- |---|-|--------->| \ _________ _________ | |___ | | | |op_clk0| | | | | | | | | | |MUX|----| PSR |----| RFS |--cdclk | | | | | | |_______| |_______| | | | |--------->| / | | | op_clk1 | / | | | |_ / | | |___________________________________________| | |-----> To other FSD SoC Peripherals In FSD I2S, the clock source is not an independent source but a common clock source being shared by many IPs in the same domain. Changing the clock tree will impact other IPs in the domain as they are dependent on the same source for functionality. We can understand your point to bring the PSR changes under the I2S CPU DAI driver by adding a separate compatible and data for the FSD SoC. But If we take the example of existing sound cards such as sound/soc/samsung/tm2_wm5110.c, the op_clk is supplied via external audio pll to the controller and PLL configuration is taken care by the sound card. Since the configuration of PLL is more specific to the tm2 platform, it makes use of the flexibility of changing the RFS and BFS using the sysclk and clkdiv hooks provided by exynos7-i2s CPU DAI along with PLL tuning for precise sampling frequency. Similar to the above example, the choice of clock source under discussion is not a limitation of exynos7-i2s controller, but instead is a limitation on the FSD SoC. By using the proposed change, we can ensure that the exynos CPU DAI driver is giving additional hooks similar to existing hooks for BFS, RFS and CDCLK direction so that sound cards can use snd_soc_dai_set_sysclk and snd_soc_dai_set_clkdiv to customize the same. An alternative approach is to use the cpu dai as bit clock and frame clock consumer (i.e. in slave mode) so that codec can supply the MCLK to FSD for playback and capture. But this will deviate from the actual usecase for FSD SoC, where the CPU DAI is intended to function as master.
