On 22. 10. 14. 00:13, David Virag wrote:
> "div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by
> 2 to achieve a by 4 division, thus their parents are the respective
> "div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents.
> This leads to the kernel thinking "div4"s and everything under them run
> at 2x the clock speed. Fix this.
>
> Fixes: 45bd8166a1d8 ("clk: samsung: Add initial Exynos7885 clock driver")
> Signed-off-by: David Virag <virag.david003@xxxxxxxxx>
> ---
> drivers/clk/samsung/clk-exynos7885.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk-exynos7885.c
> index a7b106302706..368c50badd15 100644
> --- a/drivers/clk/samsung/clk-exynos7885.c
> +++ b/drivers/clk/samsung/clk-exynos7885.c
> @@ -182,7 +182,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
> CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
> DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll",
> CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
> - DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "fout_shared0_pll",
> + DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
> CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
> DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll",
> CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
> @@ -190,7 +190,7 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
> CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
> DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll",
> CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
> - DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "fout_shared1_pll",
> + DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
> CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
>
> /* CORE */
Acked-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx>
Thanks for fix-up.
--
Best Regards,
Samsung Electronics
Chanwoo Choi
