On 22. 7. 27. 15:01, Chanho Park wrote:
> CMU_FSYS1 provides clocks for USB(2 x USB3.1 Gen-1, 2 x USB 2.0) and
> mmc. For MMC clocks, PLL_MMC(PLL0831X type) is also supported as a PLL
> source clock provider.
>
> Signed-off-by: Chanho Park <chanho61.park@xxxxxxxxxxx>
> ---
> drivers/clk/samsung/clk-exynosautov9.c | 129 +++++++++++++++++++++++++
> 1 file changed, 129 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
> index 527a6837661e..b61eec1244cc 100644
> --- a/drivers/clk/samsung/clk-exynosautov9.c
> +++ b/drivers/clk/samsung/clk-exynosautov9.c
> @@ -1307,6 +1307,132 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
> .clk_name = "dout_clkcmu_fsys0_bus",
> };
>
> +/* ---- CMU_FSYS1 ---------------------------------------------------------- */
> +
> +/* Register Offset definitions for CMU_FSYS1 (0x17040000) */
> +#define PLL_LOCKTIME_PLL_MMC 0x0000
> +#define PLL_CON0_PLL_MMC 0x0100
> +#define PLL_CON3_PLL_MMC 0x010c
> +#define PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER 0x0600
> +#define PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER 0x0610
> +#define PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER 0x0620
> +
> +#define CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD 0x1000
> +#define CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD 0x1800
> +
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2018
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x202c
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2028
> +
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40 0x204c
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40 0x2058
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40 0x2064
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40 0x2070
> +
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK 0x2074
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK 0x2078
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK 0x207c
> +#define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK 0x2080
> +
> +static const unsigned long fsys1_clk_regs[] __initconst = {
> + PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER,
> +};
> +
> +static const struct samsung_pll_clock fsys1_pll_clks[] __initconst = {
> + PLL(pll_0831x, FOUT_MMC_PLL, "fout_mmc_pll", "oscclk",
> + PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL),
> +};
> +
> +/* List of parent clocks for Muxes in CMU_FSYS1 */
> +PNAME(mout_fsys1_bus_user_p) = { "oscclk", "dout_clkcmu_fsys1_bus" };
> +PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
> +PNAME(mout_fsys1_mmc_card_user_p) = { "oscclk", "gout_clkcmu_fsys1_mmc_card" };
> +PNAME(mout_fsys1_usbdrd_user_p) = { "oscclk", "dout_clkcmu_fsys1_usbdrd" };
> +PNAME(mout_fsys1_mmc_card_p) = { "mout_fsys1_mmc_card_user", "mout_mmc_pll" };
> +
> +static const struct samsung_mux_clock fsys1_mux_clks[] __initconst = {
> + MUX(CLK_MOUT_FSYS1_BUS_USER, "mout_fsys1_bus_user",
> + mout_fsys1_bus_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER, 4, 1),
> + MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p,
> + PLL_CON0_PLL_MMC, 4, 1),
> + MUX(CLK_MOUT_FSYS1_MMC_CARD_USER, "mout_fsys1_mmc_card_user",
> + mout_fsys1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER,
> + 4, 1),
> + MUX(CLK_MOUT_FSYS1_USBDRD_USER, "mout_fsys1_usbdrd_user",
> + mout_fsys1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER,
> + 4, 1),
> + MUX(CLK_MOUT_FSYS1_MMC_CARD, "mout_fsys1_mmc_card",
> + mout_fsys1_mmc_card_p, CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD,
> + 0, 1),
> +};
> +
> +static const struct samsung_div_clock fsys1_div_clks[] __initconst = {
> + DIV(CLK_DOUT_FSYS1_MMC_CARD, "dout_fsys1_mmc_card",
> + "mout_fsys1_mmc_card",
> + CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD, 0, 9),
> +};
> +
> +static const struct samsung_gate_clock fsys1_gate_clks[] __initconst = {
> + GATE(CLK_GOUT_FSYS1_PCLK, "gout_fsys1_pclk", "mout_fsys1_bus_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
> + 21, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN, "gout_fsys1_mmc_card_sdclkin",
> + "dout_fsys1_mmc_card",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
> + 21, CLK_SET_RATE_PARENT, 0),
> + GATE(CLK_GOUT_FSYS1_MMC_CARD_ACLK, "gout_fsys1_mmc_card_aclk",
> + "dout_fsys1_mmc_card",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB20DRD_0_REFCLK, "gout_fsys1_usb20drd_0_refclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB20DRD_1_REFCLK, "gout_fsys1_usb20drd_1_refclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB30DRD_0_REFCLK, "gout_fsys1_usb30drd_0_refclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB30DRD_1_REFCLK, "gout_fsys1_usb30drd_1_refclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB20_0_ACLK, "gout_fsys1_usb20_0_aclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB20_1_ACLK, "gout_fsys1_usb20_1_aclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB30_0_ACLK, "gout_fsys1_usb30_0_aclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_FSYS1_USB30_1_ACLK, "gout_fsys1_usb30_1_aclk",
> + "mout_fsys1_usbdrd_user",
> + CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK,
> + 21, 0, 0),
> +};
> +
> +static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
> + .pll_clks = fsys1_pll_clks,
> + .nr_pll_clks = ARRAY_SIZE(fsys1_pll_clks),
> + .mux_clks = fsys1_mux_clks,
> + .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
> + .div_clks = fsys1_div_clks,
> + .nr_div_clks = ARRAY_SIZE(fsys1_div_clks),
> + .gate_clks = fsys1_gate_clks,
> + .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
> + .nr_clk_ids = FSYS1_NR_CLK,
> + .clk_regs = fsys1_clk_regs,
> + .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
> + .clk_name = "dout_clkcmu_fsys1_bus",
> +};
> +
> /* ---- CMU_FSYS2 ---------------------------------------------------------- */
>
> /* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
> @@ -1944,6 +2070,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = {
> }, {
> .compatible = "samsung,exynosautov9-cmu-fsys0",
> .data = &fsys0_cmu_info,
> + }, {
> + .compatible = "samsung,exynosautov9-cmu-fsys1",
> + .data = &fsys1_cmu_info,
> }, {
> .compatible = "samsung,exynosautov9-cmu-fsys2",
> .data = &fsys2_cmu_info,
Acked-by: Chanwoo Choi <cw00.choi@xxxxxxxxxxx>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
