On Fri, 2022-06-24 at 09:59 +0200, Krzysztof Kozlowski wrote:
> On 26/05/2022 09:21, Krzysztof Kozlowski wrote:
> > On 26/05/2022 07:58, David Virag wrote:
> > > "div4" DIVs which divide PLLs by 4 are actually dividing "div2"
> > > DIVs by
> > > 2 to achieve a by 4 division, thus their parents are the
> > > respective
> > > "div2" DIVs. These DIVs were mistakenly set to have the PLLs as
> > > parents.
> > > This leads to the kernel thinking "div4"s and everything under
> > > them run
> > > at 2x the clock speed. Fix this.
> > >
> > > Fixes: 45bd8166a1d8 ("clk: samsung: Add initial Exynos7885 clock
> > > driver")
> > > Signed-off-by: David Virag <virag.david003@xxxxxxxxx>
> > > ---
> > > drivers/clk/samsung/clk-exynos7885.c | 4 ++--
> > > 1 file changed, 2 insertions(+), 2 deletions(-)
>
> Sylwester,
>
> This goes to v5.20?
>
> Best regards,
> Krzysztof
Hi Krzysztof and Sylwester,
What is going on with this patch? What will happen to it? From what
I've seen, Sylwester doesn't seem to be too active lately. I just don't
want it to get lost. With only one of the patches applied, UART is
partially broken on 7885. Don't want to make unnecessary noise, but
this patch should probably be applied sooner than later.
Best regards,
David
