> In new Exynos SoCs (like Exynos850) where HSI2C is implemented as a part > of USIv2 block, there are two clocks provided to HSI2C controller: > - PCLK: bus clock (APB), provides access to register interface > - IPCLK: operating IP-core clock; SCL is derived from this one > > Both clocks have to be asserted for HSI2C to be functional in that case. > > Add code to obtain and enable/disable PCLK in addition to already handled > operating clock. Make it optional though, as older Exynos SoC variants > only have one HSI2C clock. > > Signed-off-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx> Reviewed-by: Chanho Park <chanho61.park@xxxxxxxxxxx> Best Regards, Chanho Park
