Exynos850 is a bit different from SoCs already supported in WDT driver:
- AUTOMATIC_WDT_RESET_DISABLE register is removed, so its value is
always 0; .disable_auto_reset callback is not set for that reason
- MASK_WDT_RESET_REQUEST register is replaced with
CLUSTERx_NONCPU_IN_EN register; instead of masking (disabling) WDT
reset interrupt it's now enabled with the same value; .mask_reset
callback is reused for that functionality though
- To make WDT functional, WDT counter needs to be enabled in
CLUSTERx_NONCPU_OUT register; it's done using .enable_counter
callback
Also Exynos850 has two CPU clusters, each has its own dedicated WDT
instance. It takes two different driver data structures (and thus two
different compatibles), as for each cluster there are different
registers and different bits used.
Signed-off-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
---
drivers/watchdog/s3c2410_wdt.c | 49 ++++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index bfc5872ca497..ca082b1226e3 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -56,6 +56,10 @@
#define EXYNOS5_RST_STAT_REG_OFFSET 0x0404
#define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408
#define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c
+#define EXYNOS850_CLUSTER0_NONCPU_OUT 0x1220
+#define EXYNOS850_CLUSTER0_NONCPU_INT_EN 0x1244
+#define EXYNOS850_CLUSTER1_NONCPU_OUT 0x1620
+#define EXYNOS850_CLUSTER1_NONCPU_INT_EN 0x1644
#define QUIRK_HAS_PMU_CONFIG (1 << 0)
#define QUIRK_HAS_RST_STAT (1 << 1)
#define QUIRK_HAS_WTCLRINT_REG (1 << 2)
@@ -141,6 +145,7 @@ struct s3c2410_wdt {
static int s3c2410wdt_disable_wdt_reset(struct s3c2410_wdt *wdt, bool mask);
static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask);
+static int s3c2410wdt_enable_wdt_reset(struct s3c2410_wdt *wdt, bool mask);
static int s3c2410wdt_enable_counter(struct s3c2410_wdt *wdt, bool en);
static const struct s3c2410_wdt_variant drv_data_s3c2410 = {
@@ -188,6 +193,32 @@ static const struct s3c2410_wdt_variant drv_data_exynos7 = {
.mask_reset = s3c2410wdt_mask_wdt_reset,
};
+static const struct s3c2410_wdt_variant drv_data_exynos850_cl0 = {
+ .mask_reset_reg = EXYNOS850_CLUSTER0_NONCPU_INT_EN,
+ .mask_bit = 2,
+ .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
+ .rst_stat_bit = 24, /* CLUSTER0 WDTRESET */
+ .cnt_en_reg = EXYNOS850_CLUSTER0_NONCPU_OUT,
+ .cnt_en_bit = 7,
+ .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
+ | QUIRK_HAS_WTCLRINT_REG,
+ .mask_reset = s3c2410wdt_enable_wdt_reset,
+ .enable_counter = s3c2410wdt_enable_counter,
+};
+
+static const struct s3c2410_wdt_variant drv_data_exynos850_cl1 = {
+ .mask_reset_reg = EXYNOS850_CLUSTER1_NONCPU_INT_EN,
+ .mask_bit = 2,
+ .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
+ .rst_stat_bit = 23, /* CLUSTER1 WDTRESET */
+ .cnt_en_reg = EXYNOS850_CLUSTER1_NONCPU_OUT,
+ .cnt_en_bit = 7,
+ .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
+ | QUIRK_HAS_WTCLRINT_REG,
+ .mask_reset = s3c2410wdt_enable_wdt_reset,
+ .enable_counter = s3c2410wdt_enable_counter,
+};
+
static const struct of_device_id s3c2410_wdt_match[] = {
{ .compatible = "samsung,s3c2410-wdt",
.data = &drv_data_s3c2410 },
@@ -199,6 +230,10 @@ static const struct of_device_id s3c2410_wdt_match[] = {
.data = &drv_data_exynos5420 },
{ .compatible = "samsung,exynos7-wdt",
.data = &drv_data_exynos7 },
+ { .compatible = "samsung,exynos850-cl0-wdt",
+ .data = &drv_data_exynos850_cl0 },
+ { .compatible = "samsung,exynos850-cl1-wdt",
+ .data = &drv_data_exynos850_cl1 },
{},
};
MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
@@ -254,6 +289,20 @@ static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask)
return ret;
}
+static int s3c2410wdt_enable_wdt_reset(struct s3c2410_wdt *wdt, bool mask)
+{
+ const u32 mask_val = 1 << wdt->drv_data->mask_bit;
+ const u32 val = mask ? 0 : mask_val; /* reset interrupt enable value */
+ int ret;
+
+ ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->mask_reset_reg,
+ mask_val, val);
+ if (ret < 0)
+ dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
+
+ return ret;
+}
+
static int s3c2410wdt_enable_counter(struct s3c2410_wdt *wdt, bool en)
{
const u32 mask_val = 1 << wdt->drv_data->cnt_en_bit;
--
2.30.2
