Hi Arnd and Olof, I have an old patchset for RISC-V dts cleanups which I sent to mailing lists in August 2021 (v1, v2), resent in September and pinged two times. They got some review (from Alexandre Ghiti for SiFive, from Conor Dooley for Microchip) but unfortunately Palmer (RISC-V maintainer) did not respond here. The usual RISC-V patches go via Palmer to Linus and I am not planning to change that, but I want to get these fixed. Could you grab these to soc tree? Best regards, Krzysztof The following changes since commit 6880fa6c56601bb8ed59df6c30fd390cc5f6dd8f: Linux 5.15-rc1 (2021-09-12 16:28:37 -0700) are available in the Git repository at: https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/riscv-sifive-dt-5.16 for you to fetch changes up to 9962a066f3c1d4588d0dd876ceac2c03ef87acf3: riscv: dts: sifive: add missing compatible for plic (2021-10-19 10:59:57 +0200) ---------------------------------------------------------------- RISC-V DTS changes for v5.16 Cleanups of RISC-V SiFive and Microchip DTSes with dtschema. These are few minor fixes to make DTSes pass the dtschema, without actual functional effect. ---------------------------------------------------------------- Krzysztof Kozlowski (5): riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible riscv: dts: sifive: fix Unleashed board compatible riscv: dts: sifive: drop duplicated nodes and properties in sifive riscv: dts: microchip: add missing compatibles for clint and plic riscv: dts: sifive: add missing compatible for plic arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 4 ++-- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 2 +- arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 10 +++------- arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 7 +------ 4 files changed, 7 insertions(+), 16 deletions(-)
