> > +static int exynosauto_ufs_post_hce_enable(struct exynos_ufs *ufs) {
> > + struct ufs_hba *hba = ufs->hba;
> > +
> > + /* Enable Virtual Host #1 */
> > + ufshcd_rmwl(hba, MHCTRL_EN_VH_MASK, MHCTRL_EN_VH(1), MHCTRL);
> > + /* Default VH Transfer permissions */
> > + hci_writel(ufs, ALLOW_TRANS_VH_DEFAULT,
> > HCI_MH_ALLOWABLE_TRAN_OF_VH);
> > + /* IID information is replaced in TASKTAG[7:5] instead of IID in
> UCD */
> > + hci_writel(ufs, 0x1, HCI_MH_IID_IN_TASK_TAG);
> If I understand correctly, once you set this register, the hw takes care
> of properly arbitrating the requests - PH + up to 4 VHs total of 5
> machines, each supporting 32 requests doorbell.
Actually, four Multi Hosts (1 for PH and 3 for VHs)
> Can you share what policy the arbiter uses among the 5 doorbells?
AFAIK, it is working something like round-robin. It also has a full checker so it will be acting as the RR arbiter until the requests are full not to be handled by the controller (I'm not sure the exact number of the full count). If full, the lowest UTRD idx will be first.
>
> You are designating this change to be used in a UFS2.1 platforms, correct?
Yes.
> Are you planning to use the same framework for UFSHCI4.0, which uses MCQ?
AFAIK, next chip will be compatible with 3.1 not 4.0.
Best Regards,
Chanho Park
