> > > > + sysreg: > > > > > > Needs a vendor prefix. > > > > Thanks. I'll use "samsung,sysreg-phandle". > > No '-phandle'. Will use "samsung,sysreg" next patch series. > > > > > > > > > > + $ref: '/schemas/types.yaml#/definitions/phandle' > > > > + description: phandle for FSYS sysreg interface, used to control > > > > + sysreg register bit for UFS IO Coherency > > > > > > Is there more than 1 FSYS? If not, you can just get the node by its > > > compatible. > > > > The phandle can be differed each exynos SoCs, AFAIK. I think other > > exynos SoCs since exnos7 will need this but not upstreamed yet... > > That's still fine. You really only need a phandle if there is more than > 1 instance on a given platform. > > Of course you could end up with multiple compatible strings to deal with, > but you might need that anyway as the registers are likely to be different. > That can sometimes be mitigated by putting register offsets into the DT > property (something to consider here). This is the problem with drivers > directly twiddling bits in other h/w blocks and why we have common > interfaces for clocks, resets, etc. Regarding ufs-exynos, it can have multiple instances (ufs_0/1/22). I'm also preparing to support ufs_1 for exynosautov9 SoC but not yet finished due to ufs phy control. Each instances has their own sysreg offset. To support secondary ufs, I need to rework this patch and add the offset field as DT propery. +#define UFS_SHAREABILITY_OFFSET 0x710 For UFS1, this should be 0x714. > > I leave it to you to decide how you want to do it. > > BTW, If you want to see another way to handle the same problem, see > highbank_platform_notifier(). Notifiers aren't great either, but it keeps > some SoC specifics out of the driver. > I checked highbank_platform_notifier() implementation but I need to keep this way to have further support multiple ufs instances and can be used for exynos8/9 SoCs as well. Best Regards, Chanho Park
