On Wed, 04 Aug 2021 15:39:38 +0100,
Sam Protsenko <semen.protsenko@xxxxxxxxxx> wrote:
> > You are also missing the hypervisor virtual timer interrupt.
> >
>
> Checked SoC TRM, there is no PPI for hypervisor virtual timer
> interrupt, and no mentioning of it at all. Likewise, I checked ARMv8
> ARM and TRM, almost no description of it. Also, I checked other
> platforms, and seems like everyone does the same (having only 4
> interrupts). And I wasn't able to find any documentation on that, so I
> guess I'll leave it as is, if you don't mind.
I *do* mind, and other DTs being wrong isn't a good enough excuse! ;-)
>From the ARMv8 ARM (ARM DDI 0487G.b)
<quote>
D11.2.4 Timers
In an implementation of the Generic Timer that includes EL3, if EL3
can use AArch64, the following timers are implemented:
* An EL1 physical timer, that:
- In Secure state, can be accessed from EL1.
- In Non-secure state, can be accessed from EL1 unless those
accesses are trapped to EL2.
When this timer can be accessed from EL1, an EL1 control
determines whether it can be accessed from EL0.
* A Non-secure EL2 physical timer.
* A Secure EL3 physical timer. An EL3 control determines whether this
register is accessible from Secure EL1.
* An EL1 virtual timer.
* When FEAT_VHE is implemented, a Non-secure EL2 virtual timer.
* When FEAT_SEL2 is implemented, a Secure EL2 physical timer.
* When FEAT_SEL2 is implemented, a Secure EL2 virtual timer.
</quote>
Cortex-A55 being an ARMv8.2 implementation, it has FEAT_VHE, and thus
it does have a NS-EL2 virtual timer. This is further confirmed by the
TRM which documents CNTHV*_EL2 as valid system registers[1].
So the timer exists, the signal is routed out of the core, and it
is likely that it is connected to the GIC.
If the designers have omitted it, then it needs to be documented as
such.
Thanks,
M.
[1] https://developer.arm.com/documentation/100442/0100/register-descriptions/aarch64-system-registers/aarch64-architectural-system-register-summary
--
Without deviation from the norm, progress is not possible.
