On 17/06/2021 13:37, Alim Akhtar wrote:
> This patch adds cpu caches information to its dt
> nodes so that the same is available to userspace
> via sysfs.
> This SoC has 48/32 KB I/D cache for each A57 cores
> with 2MB L2 cache.
> And 32/32 KB I/D cache for each A53 cores with
> 256KB L2 cache.
>
> Signed-off-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 70 ++++++++++++++++++++++
> 1 file changed, 70 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index 18a912eee360..8183a59e9046 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -62,6 +62,13 @@
> clock-names = "apolloclk";
> operating-points-v2 = <&cluster_a53_opp_table>;
> #cooling-cells = <2>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&apollo_l2>;
> };
>
> cpu1: cpu@101 {
> @@ -72,6 +79,13 @@
> clock-frequency = <1300000000>;
> operating-points-v2 = <&cluster_a53_opp_table>;
> #cooling-cells = <2>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&apollo_l2>;
> };
>
> cpu2: cpu@102 {
> @@ -82,6 +96,13 @@
> clock-frequency = <1300000000>;
> operating-points-v2 = <&cluster_a53_opp_table>;
> #cooling-cells = <2>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&apollo_l2>;
> };
>
> cpu3: cpu@103 {
> @@ -92,6 +113,13 @@
> clock-frequency = <1300000000>;
> operating-points-v2 = <&cluster_a53_opp_table>;
> #cooling-cells = <2>;
> + i-cache-size = <0x8000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <128>;
> + next-level-cache = <&apollo_l2>;
> };
>
> cpu4: cpu@0 {
> @@ -104,6 +132,13 @@
> clock-names = "atlasclk";
> operating-points-v2 = <&cluster_a57_opp_table>;
> #cooling-cells = <2>;
> + i-cache-size = <0xc000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&atlas_l2>;
> };
>
> cpu5: cpu@1 {
> @@ -114,6 +149,13 @@
> clock-frequency = <1900000000>;
> operating-points-v2 = <&cluster_a57_opp_table>;
> #cooling-cells = <2>;
> + i-cache-size = <0xc000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&atlas_l2>;
> };
>
> cpu6: cpu@2 {
> @@ -124,6 +166,13 @@
> clock-frequency = <1900000000>;
> operating-points-v2 = <&cluster_a57_opp_table>;
> #cooling-cells = <2>;
> + i-cache-size = <0xc000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&atlas_l2>;
> };
>
> cpu7: cpu@3 {
> @@ -134,6 +183,27 @@
> clock-frequency = <1900000000>;
> operating-points-v2 = <&cluster_a57_opp_table>;
> #cooling-cells = <2>;
> + i-cache-size = <0xc000>;
> + i-cache-line-size = <64>;
> + i-cache-sets = <256>;
> + d-cache-size = <0x8000>;
> + d-cache-line-size = <64>;
> + d-cache-sets = <256>;
> + next-level-cache = <&atlas_l2>;
> + };
> +
> + atlas_l2: l2-cache0 {
Few other nodes (PMU, OPP tables) use a57/a53 names instead of
codenames, so I would prefer to stay with them (so cluster_a57_l2).
For Exynos7 it's fine as it uses Atlas already in labels.
> + compatible = "cache";
> + cache-size = <0x200000>;
> + cache-line-size = <64>;
> + cache-sets = <2048>;
> + };
> +
> + apollo_l2: l2-cache1 {
> + compatible = "cache";
> + cache-size = <0x40000>;
> + cache-line-size = <64>;
> + cache-sets = <256>;
> };
> };
>
>
Best regards,
Krzysztof
