On Fri, Mar 12, 2021 at 04:57:07PM -0800, Randy Dunlap wrote:
> On 3/12/21 4:50 PM, Bhaskar Chowdhury wrote:
> > On 17:16 Fri 12 Mar 2021, Tom Saeger wrote:
> >> On Sat, Mar 13, 2021 at 04:56:21AM +0530, Bhaskar Chowdhury wrote:
> >>
> >> sent a few additional typo fixes to your V1, can you add those to your patch?
> >>
> >> Regards,
> >>
> >> --Tom
> >
> > Thanks, I have already sent out a V2 in public...I might make a V3 with your
> > changes too...did you sent it to ???
>
> It was just a reply to your v1 patch.
>
> --
> ~Randy
>
Bhaskar,
Here you go...
V2 additions:
diff --git a/drivers/cpufreq/s5pv210-cpufreq.c b/drivers/cpufreq/s5pv210-cpufreq.c
index af1ac3f6e4b8..73110b005716 100644
--- a/drivers/cpufreq/s5pv210-cpufreq.c
+++ b/drivers/cpufreq/s5pv210-cpufreq.c
@@ -91,7 +91,7 @@ static DEFINE_MUTEX(set_freq_lock);
/* Use 800MHz when entering sleep mode */
#define SLEEP_FREQ (800 * 1000)
-/* Tracks if cpu freqency can be updated anymore */
+/* Tracks if cpu frequency can be updated anymore */
static bool no_cpufreq_access;
/*
@@ -190,7 +190,7 @@ static u32 clkdiv_val[5][11] = {
/*
* This function set DRAM refresh counter
- * accoriding to operating frequency of DRAM
+ * according to operating frequency of DRAM
* ch: DMC port number 0 or 1
* freq: Operating frequency of DRAM(KHz)
*/
@@ -320,7 +320,7 @@ static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
/*
* 3. DMC1 refresh count for 133Mhz if (index == L4) is
- * true refresh counter is already programed in upper
+ * true refresh counter is already programmed in upper
* code. 0x287@83Mhz
*/
if (!bus_speed_changing)
