On Sat, Mar 13, 2021 at 04:46:20AM +0530, Bhaskar Chowdhury wrote:
> On 15:01 Fri 12 Mar 2021, Krzysztof Kozlowski wrote:
> > On 12/03/2021 13:08, Bhaskar Chowdhury wrote:
> > >
> > > s/untile/until/
> > > s/souce/source/
> > > s/divier/divider/
> > >
> > > Signed-off-by: Bhaskar Chowdhury <unixbhaskar@xxxxxxxxx>
> > > ---
> > > drivers/cpufreq/s5pv210-cpufreq.c | 6 +++---
> > > 1 file changed, 3 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/cpufreq/s5pv210-cpufreq.c b/drivers/cpufreq/s5pv210-cpufreq.c
> > > index bed496cf8d24..1cfea5339beb 100644
> > > --- a/drivers/cpufreq/s5pv210-cpufreq.c
> > > +++ b/drivers/cpufreq/s5pv210-cpufreq.c
> > > @@ -378,7 +378,7 @@ static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
> > > /*
> > > * 6. Turn on APLL
> > > * 6-1. Set PMS values
> > > - * 6-2. Wait untile the PLL is locked
> > > + * 6-2. Wait until the PLL is locked
> > > */
> > > if (index == L0)
> > > writel_relaxed(APLL_VAL_1000, S5P_APLL_CON);
> > > @@ -390,7 +390,7 @@ static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
> > > } while (!(reg & (0x1 << 29)));
> > >
> > > /*
> > > - * 7. Change souce clock from SCLKMPLL(667Mhz)
> > > + * 7. Change source clock from SCLKMPLL(667Mhz)
> > > * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
> > > * (667/4=166)->(200/4=50)Mhz
> > > */
> > > @@ -439,7 +439,7 @@ static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
> > > }
> > >
> > > /*
> > > - * L4 level need to change memory bus speed, hence onedram clock divier
> > > + * L4 level need to change memory bus speed, hence onedram clock divider
> >
> > Also grammar fix: need/needs.
> >
> Hmmm ...good catch...V2 on the way...
>
> > Best regards,
> > Krzysztof
May as well roll in few more?
Regards,
--Tom
diff --git a/drivers/cpufreq/s5pv210-cpufreq.c b/drivers/cpufreq/s5pv210-cpufreq.c
index a186c0d8a290..6ecef301bd40 100644
--- a/drivers/cpufreq/s5pv210-cpufreq.c
+++ b/drivers/cpufreq/s5pv210-cpufreq.c
@@ -91,7 +91,7 @@ static DEFINE_MUTEX(set_freq_lock);
/* Use 800MHz when entering sleep mode */
#define SLEEP_FREQ (800 * 1000)
-/* Tracks if cpu freqency can be updated anymore */
+/* Tracks if cpu frequency can be updated anymore */
static bool no_cpufreq_access;
/*
@@ -190,7 +190,7 @@ static u32 clkdiv_val[5][11] = {
/*
* This function set DRAM refresh counter
- * accoriding to operating frequency of DRAM
+ * according to operating frequency of DRAM
* ch: DMC port number 0 or 1
* freq: Operating frequency of DRAM(KHz)
*/
@@ -320,7 +320,7 @@ static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
/*
* 3. DMC1 refresh count for 133Mhz if (index == L4) is
- * true refresh counter is already programed in upper
+ * true refresh counter is already programmed in upper
* code. 0x287@83Mhz
*/
if (!bus_speed_changing)
