On Wed, 2 Dec 2020 13:20:29 +0100, Marek Szyprowski wrote:
> Commit 2024b130b0c8 ("ARM: dts: exynos: Add Ethernet to Artik 5 board")
> added ethernet chip on SPI0 bus and the whole bunch of assigned clock
> entries to ensure proper clock rates and topology. Limit the assigned
> clock parents only to the direct clocks of the SPI0 device and assume
> that MPLL clock is already properly configured.
>
> The applied clock topology was incorrect as some clocks between were
> missing, what resulted in the following warning:
>
> [...]
Applied, thanks!
[1/1] ARM: dts: exynos: Reduce assigned-clocks entries for SPI0 on Artik5 board
commit: 7995fb896b9637a5f59a56ae0d8f2b7ca71a040d
Best regards,
--
Krzysztof Kozlowski <krzk@xxxxxxxxxx>
